后端设计工程师岗位职责（4篇范文）

第1篇 后端设计工程师岗位职责

ic后端设计工程师 南京华捷艾米 南京华捷艾米软件科技有限公司,华捷艾米,南京华捷艾米,南京华捷艾米 responsibilities:

responsible for all aspects of chip backend design, including floor planning, place and routing, cts, timing convergence iterations/optimization, and final drc/lvs.

qualifications:

1. bsee, msee or higher.

2. at least 2 years experience of large asic backend designs.

3. experience with synopsys and/or cadence design tools.

4. have 65/40/28nm experience is better.

5. good communication skills, team spirit.

工作职责:

负责整个芯片或模块的布局布线设计, 包括布局规划, 布局布线, 时钟树生成, 时序优化和收敛, 以及 drc/lvs物理验证.

任职资格:

1. 电子工程或微电子专业本科及以上学历;

2. 至少2年以上大规模集成电路芯片后端设计经验;

3. 具有使用synopsys 或cadence 设计工具的相关经验;

4. 最好有65/40/28nm设计经验;

5. 良好沟通能力和团队精神。

第2篇 ic后端设计工程师岗位职责

ic后端设计工程师 南京华捷艾米 南京华捷艾米软件科技有限公司,华捷艾米,南京华捷艾米,南京华捷艾米 responsibilities:

responsible for all aspects of chip backend design, including floor planning, place and routing, cts, timing convergence iterations/optimization, and final drc/lvs.

qualifications:

1. bsee, msee or higher.

2. at least 2 years experience of large asic backend designs.

3. experience with synopsys and/or cadence design tools.

4. have 65/40/28nm experience is better.

5. good communication skills, team spirit.

工作职责:

负责整个芯片或模块的布局布线设计, 包括布局规划, 布局布线, 时钟树生成, 时序优化和收敛, 以及 drc/lvs物理验证.

任职资格:

1. 电子工程或微电子专业本科及以上学历;

2. 至少2年以上大规模集成电路芯片后端设计经验;

3. 具有使用synopsys 或cadence 设计工具的相关经验;

4. 最好有65/40/28nm设计经验;

5. 良好沟通能力和团队精神。

第3篇 数字后端设计工程师岗位职责

数字后端设计工程师 西安紫光国芯半导体有限公司 西安紫光国芯半导体有限公司,华芯半导体,西安紫光国芯,西安紫光国芯半导体有限公司,紫光国芯 asic backend design engineer (be)

数字后端设计工程师

responsibilities:

1. responsible for developing digital designs with emphasis on backend, including floor-plan, power planning, place, cts and route.

2. work with front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.

3. optimization and verification of layout for tape-out (including rc extraction, eco, drc, lvs).

4. power ir drop analysis and optimization, area and parasitic layout optimization, chip size optimization.

5. static timing analysis (prime time) and setup/hold fix.

6. formal verification for equivalence checking (formality).

7. generation of fill structures according to technology requirements.

requirements:

1. 4 years experience in backend design flow (apr) with proven soc tape-out experience.

2. experienced in synopsys/cadence automatically physical implementation tools and flows (ic-compiler/ astro / soc-encounter/ milky-way/ star-rcx) is a plus.

3. experience with one or more scripting languages (perl, tcl, or shell) to make reusable automatically flow is a plus.

4. experience and knowledge about fe design (rtl code, flow) and verification is a plus.

5. good analytical and debugging skills.

6. good command of english.

第4篇 芯片后端设计工程师岗位职责

工作职责

负责asic/soc芯片的物理实现及推动项目按时保质完成,主要包括:主导floorplan,placement&routing,power planning,physical verification, top & block level timing closure; function and timing eco等方面的具体实现工作;负责与前端设计团队、foundry/design service/test&package/ip vendor的沟通,并推动所有问题按时解决;负责推动项目的后端整体进度,并顺利投片。

工作要求

一本全日制本科或硕士毕业,从事芯片物理设计3年以上, 熟悉rtl设计和验证基本流程;熟悉lint和cdc相关工具; 熟悉物理设计流程;具有丰富的顶层floorplan经验;具有丰富的placement&routing经验;具有low power, dft, sta, em/ir-drop/si analysis, lec, physical verification, dfm等方面扎实的理论和实践基础;具有28nm以下工艺节点流片经验者优先。